Time-to-Digital Converter in Advanced CMOS Technology

Project Description

Precise Time stamping is a key performance in numbers of applications, such as time-of-flight Positron Emission Tomography (PET), Quantum Key Distribution (QKD), Lidar and various physic experiments. The goal pursued by our group is to achieve a timing resolution below 10 ps Full Width at Half Maximum (FWHM) with the complete system, including the photosensors and all the subsequent electronics. One of the key elements is the time digitizer, namely Time-to-Digital Converter (TDC), that needs to provide a level of performance well beyond the state-of-the-art in terms of timing performance, power consumption and size. Our group has a great expertise in TDC designs [1][2], and we strongly believe that with advanced CMOS technology and the proper TDC architecture, we can improve significantly the performance reached currently in such a system.

This project will require to design and send to fabrication the Time-to-Digital Converter and all its calibration circuits in a small node technology. Multilayer Printed Circuit Boards (PCB) and data processing will need to be designed as well. The ASIC will be tested in our facility at Interdisciplinary Institute for Technological Innovation (3IT) where the required specialized equipments (e.g. 13 GHz oscilloscope, PCB assembly line, cryogenic chambers, etc.) will be available.

This project will allow the interested person to develop knowledge in complex integrated circuits. 100% of our students found a job before or at the end of their studies. The working environment at 3IT provides the experts, infrastructure and a motivated team required for the project.

[1] N. Roy; F. Nolet; F. Dubois; M.-A. Mercier; R. Fontaine; J.-F. Pratte. (2017). Low Power and Small Area,
6.9 ps RMS Time-to-Digital Converter for 3D Digital SiPM. IEEE Transactions on Radiation and Plasma
Medical Sciences. 10(6): 486-494.

[2] F. Nolet; N. Roy; S. Carrier; J. Bouchard; R. Fontaine; S.A. Charlebois; J.-F. Pratte. (2020). 22 μW, 5.1 ps
LSB, 5.5 ps RMS jitter Vernier time-to-digital converter in CMOS 65 nm for single photon avalanche diode
array. Electronics Letters. 56(9): 424-426.

Funding offered

Yes

The last update was on 12 March 2024. The University reserves the right to modify its projects without notice.