PDF-Optimization of Micropillar Microfabrication Process for Fan-Out Wafer Level Packaging (FOWLP)

Project Description

Context:
Advanced packaging technologies are at the core of the microelectronics revolution and play a key role in areas such as artificial intelligence, aerospace, and high performance computing. Among these technologies, Fan Out Wafer Level Packaging (FOWLP) stands out for its high interconnection density and efficient use of space, enabling more compact and powerful systems.
This miniaturization presents major challenges: precise chip alignment, mechanical reliability, and resistance to electromigration. This postdoctoral project aims to develop innovative processes for the fabrication of fine-pitch micropillars (<30 μm), ensuring robust interconnections compatible with an industrial die-to-wafer (D2W) flip-chip assembly environment.
You will work in a collaborative and stimulating environment within 3IT and C2MI, two centers of excellence where researchers, students, and industry partners innovate together, offering unique opportunities for professional development and global impact.

Topic:
This postdoctoral project aims to design and optimize an advanced microfabrication process for fine pitch metallic micropillars (< 30 µm), which are essential for flip chip die to wafer (D2W) assembly within advanced Fan Out Wafer Level Packaging (FOWLP) architectures.
The main tasks include:
• Defining and optimizing lithography and deposition processes to fabricate uniform Cu/Ag/Sn micropillars on a 200 mm reconstituted wafer.
• Establishing an assembly flow based on Thermal Compression Bonding (TCB) or Laser‑Assisted Bonding (LAB) for the integration of active dies.
• Performing advanced characterizations (morphology, uniformity, and interface quality) to assess interconnection reliability.
• Collaborating with IBM  Bromont to transfer these processes into industrial environments and to contribute to the development of next‑generation assembly solutions.

By the end of the postdoctoral project, the successful candidate will have established technological solutions to improve the reliability of fine-step interconnections in an industrial context, contributing to increasing the integration density and performance of FOWLP architectures for next-generation microelectronic systems.

Work Supervision:
This postdoctoral fellowship will be supervised by Prof. Dominique Drouin as part of the IBM/NSERC Research Chair in Heterogeneous Multi Chip Integration for High Performance Computing. The doctoral research will be conducted at the 3IT (Université de Sherbrooke) and the C2MI (Bromont), two centers of excellence offering state of the art facilities and a unique collaborative environment. This setting fosters innovation, hands on cleanroom training, and active participation in industrial research projects, while promoting diversity and inclusion. The successful candidate will have the opportunity to work with multidisciplinary teams and to develop skills that are highly valued in both industry and advanced research.

Desired Profile:
• PhD in materials science, microelectronics, mechanical engineering, or a related field.
• Experience in cleanroom environments with demonstrated expertise in microfabrication processes (lithography, deposition, etching).
• Skills in advanced characterization (structural, mechanical, and electrical analyses) 
• Ability to communicate in French or English, both orally and in writing.
• Autonomy, scientific rigor, and the ability to work as part of a team in a multidisciplinary environment.
• Assets: Knowledge of advanced packaging, integration processes, and high-density interconnection technologies.

Contact: inpaqt@usherbrooke.ca
Documents to provide: Cover letter, curriculum vitae, and contact information for 2 references.

Funding offered

Yes

Annual 50 000$

Partner(s)

IBM Canada Ltée.

The last update was on 15 January 2026. The University reserves the right to modify its projects without notice.