High-Density Lateral Interconnects (RDL) for Heterogeneous Integration of Large Electronic Chips

Project Description

Context:

Advanced packaging technologies are crucial for the evolution of microelectronics, enhancing performance through heterogeneous integration. Traditional methods struggle to meet the demands of high-performance computing, AI, aerospace, and defense. Fan-Out Wafer-Level Packaging (FOWLP) was developed several years ago for the integration of advanced microelectronic systems. To achieve higher, I/O counts while minimizing the routing length, a higher redistribution line (RDL) density is required with up to 3 redistribution layers, linewidths < 2 micron. However, the current semi-additive plating (SAP) process used to fabricate the RDL poses a scaling limit for line/spacing (L/S) below 5 micron. In addition, during FOWLP process, a step height can be generated between the die and mold compound, and this has been found to increase RDL parasitic resistance. Another challenge is CTE mismatch between Si dies and epoxy molding compound (EMC), which requires careful warpage management during various thermal treatment steps in Fan-Out process flow. To overcome these limitations, we propose this thesis project to fabricate a stack of ultra-fine-pitch redistribution layers (RDLs) for process (FOWLP) to integrate heterogeneous active chips (HBM, ASIC) and passive interconnect/thermal chips using a molding approach that is compatible with large chips (> 400 mm2).

Topic: 

This PhD thesis aims to explore novel strategies to push the limit of high density RDL (HD-RDL) to meet the challenges of FOWLP applications. The successful candidate will be in charge of (i) conducting a literature review of  RDL fabrication  methods and materials used in FOWLP  to understand their properties and associated challenges, (ii) selecting 2-3 candidates of commercially available organic dielectric films, (iii) developing the complete microfabrication process of the interconnects in clean room, including organic dielectric layer deposition, electronic and optical lithography, metallic thin film deposition and plasma etching using state-of-the-art microfabrication equipment; (iv) perform complete morphological and electrical characterizations of the samples to determine the fabrication quality and performance of the interconnects. Integrity validations of HD-RDL process after the interconnection of molded chips will be targeted, considering EMC surface roughness, planarization and carrier warpage requirements. These evaluations will be performed in close collaboration with IBM engineers.

Work Supervision:

This PhD thesis will be realized under the co-direction of Pr. Dominique Drouin and Pr. Serge Ecoffey, as part of the IBM/NSERC Alliance Project on Multi-Chip Heterogeneous Integration for High Performance Computing. The work will be done mainly at the Interdisciplinary Institute for Technological Innovation (3IT) at the Université de Sherbrooke and at the MiQro Innovation Collaborative Center (C2MI) in Bromont. 3IT is a unique institute in Canada, specializing in the research and development of innovative technologies for energy, electronics, robotics and health. C2MI is an international center for collaboration and innovation in the MEMS and encapsulation field. It is the essential link between applied research and the marketing of microelectronics products. The student will thus benefit from an exceptional research environment that combines students, professionals, professors and industrialists working hand-in-hand to develop the technologies of the future.


Desired Profile:
• Master’s degree in micro-nanotechnologies or materials science
• Skills in microfabrication in clean room and electrical characterizations 
• Ability to communicate in English or French both orally and in writing 
• Strong ability to adapt, be autonomous and work in a team
• Pronounced taste for design, experimental work in a clean room, research and development
• Assets: Knowledge of integration processes, advanced microelectronic packaging

Contact: jobnano@usherbrooke.ca
Starting date: September 2025
Documents to provide: Cover letter, curriculum vitae,transcripts for the past two years & contact details of 2 references

Funding offered

To be discussed

Partner(s)

IBM Canada Ltée., Centre de Collaboration MiQro Innovation (C2MI)

The last update was on 24 October 2025. The University reserves the right to modify its projects without notice.