Internship – Towards Silicon-based logic qubits


Electrostatically confined Quantum Dots (QD) in silicon technology is a prime candidate towards logical qubits and large-scale quantum computing. Indeed, silicon is the foundation of modern electronics from which more than 50 years of high-yield manufacturing of Very Large Scale Integration (VLSI) can be leveraged. Moreover, silicon represents an ideal nuclear spin-free environment for the qubits. Exceptional quantum coherence has been demonstrated with single electron spin in isotopically-enriched 28Si devices [An addressable quantum dot qubit with fault-tolerant control-fidelity, Nature nanotechnology 9, 981 (2014)]. Single-qubit gates approaching error-correction thresholds have been realized in natural silicon using the magnetic field gradient approach pioneered by PIORO-LADRIÈRE [A fault-tolerant addressable spin qubit in natural silicon quantum dot, arXiv:1602.07833]. However, the experimental demonstration of multi-qubit control in silicon qubits represents the next big challenge for the field.

This internship will focus attention on the modification of the material stack used to build the electrostatic gates defining and controlling the QDs. We are in the need to reduce the physical dimensions of the gates in order to close the gap between the multiple QDs. A low sheet resistance allied must be tuned with limitations on the thickness and noise added by the introduction of this new material. The adjustment of the recipe for the allied formation and electrical characterization at cryogenic temperatures need to be performed and documented by the intern.

Possibility of co-supervision between Physics and Electrical Engineering

Supervisor/Co-Supervisor : Michel Pioro-Ladrière, Dominique Drouin

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